An automated technique for topology and route generation of application specific on-chip interconnection networks | IEEE Conference Publication | IEEE Xplore

An automated technique for topology and route generation of application specific on-chip interconnection networks


Abstract:

Network-on-chip (NoC) has been proposed as a solution to the communication challenges of system-on-chip (SoC) design in nanoscale technologies. Application specific SoC d...Show More

Abstract:

Network-on-chip (NoC) has been proposed as a solution to the communication challenges of system-on-chip (SoC) design in nanoscale technologies. Application specific SoC design offers the opportunity for incorporating custom NoC architectures that are more suitable for a particular application, and do not necessarily conform to regular topologies. Custom NoC design in nanoscale technologies must address performance requirements, power consumption and physical layout considerations. This paper presents a novel three phase technique that i) generates a performance aware layout of the SoC, ii) maps the cores of the SoC to routers, and iii) generates a unique route for every trace that satisfies the performance and architectural constraints. We present an analysis of the quality of the results of the proposed technique by experimentation with realistic benchmarks.
Date of Conference: 06-10 November 2005
Date Added to IEEE Xplore: 19 December 2005
Print ISBN:0-7803-9254-X

ISSN Information:

Conference Location: San Jose, CA, USA

References

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