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Data-parallel simulation for fast and accurate timing validation of CMOS circuits | IEEE Conference Publication | IEEE Xplore

Data-parallel simulation for fast and accurate timing validation of CMOS circuits


Abstract:

Gate-level timing simulation of combinational CMOS circuits is the foundation of a whole array of important EDA tools such as timing analysis and power-estimation, but th...Show More

Abstract:

Gate-level timing simulation of combinational CMOS circuits is the foundation of a whole array of important EDA tools such as timing analysis and power-estimation, but the demand for higher simulation accuracy drastically increases the runtime complexity of the algorithms. Data-parallel accelerators such as Graphics Processing Units (GPUs) provide vast amounts of computing performance to tackle this problem, but require careful attention to control-flow and memory access patterns. This paper proposes the novel High-Throughput Oriented Parallel Switch-level Simulator (HiTOPS), which is especially designed to take full advantage of GPUs and provides accurate timesimulation for multi-million gate designs at an unprecedented throughput. HiTOPS models timing at transistor granularity and supports all major timing-related effects found in CMOS including pattern-dependent delay, glitch filtering and transition ramps, while achieving speedups of up to two orders of magnitude compared to traditional gate-level simulators.
Date of Conference: 02-06 November 2014
Date Added to IEEE Xplore: 08 January 2015
Electronic ISBN:978-1-4799-6278-5

ISSN Information:

Conference Location: San Jose, CA, USA

References

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