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An analog SAT solver based on a deterministic dynamical system: (Invited paper) | IEEE Conference Publication | IEEE Xplore

An analog SAT solver based on a deterministic dynamical system: (Invited paper)

Publisher: IEEE

Abstract:

Boolean Satisfiability (SAT), the first problem proven to be NP-complete, is intractable on digital computers based on the von Neumann architecture. An efficient SAT solv...View more

Abstract:

Boolean Satisfiability (SAT), the first problem proven to be NP-complete, is intractable on digital computers based on the von Neumann architecture. An efficient SAT solver can benefit many applications such as artificial intelligence, circuit design, and functional verification. Recently, a SAT solver approach based on a deterministic, continuous-time dynamical system (CTDS) was introduced [1]. This approach shows polynomial analog time-complexity on even the hardest k-SAT (k ≥ 3) problem instances, but at an energy cost dependent on exponentially growing auxiliary variables. This paper reports a novel analog hardware SAT solver, AC-SAT, implementing the CTDS via incorporating novel, analog circuit design ideas. AC-SAT is intended to be used as a co-processor and is programmable for handling different problem specifications. Furthermore, with its modular design, AC-SAT can be readily extended to solve larger size problems. SPICE simulation results show that AC-SAT can indeed solve the SAT problems, and it has speedup factors of ~10 4 on even the hardest 3-SAT problems, when compared with a state-of-the-art SAT solver on digital computers.
Date of Conference: 13-16 November 2017
Date Added to IEEE Xplore: 14 December 2017
ISBN Information:
Electronic ISSN: 1558-2434
Publisher: IEEE
Conference Location: Irvine, CA, USA

References

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