The time division multiplexing technique overcomes the bandwidth limitation by allowing FPGA chips to transmit multiple signals the maximum clocking frequency. With the additional multiplexers, this technique dramatically increases system-level routing capability in the FPGA-based emulator. However, the large number of virtual wires in the chip interconnection may impact emulation performance. The system-level FPGA routing tends to connect all virtual wires (signals) and considers emulation performance. At the same time, the challenge for system-level FPGA routing using time division multiplexing lies in the emulation performance.