For many devices, power side-channel attacks are an effective means of obtaining secret keys from cryptographic algorithms. Recently, methods have been proposed to assess the vulnerability of devices to these attacks. While existing approaches effectively evaluate device vulnerability to attacks at specific points during execution, they do not consider the power measurement vectors holistically, using all time points in the measurement. This is necessary in order to accurately assess resistance to multi-target attacks. In this work, we identify characteristics of an ideal holistic side-channel security metric and develop a metric under these criteria. We demonstrate that our approach correctly ranks different FPGA implementations of AES with respect to attack difficulty.