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Implementation of 1T1R-based OxRRAM Memristor Model for Circuit Design and Simulation | IEEE Conference Publication | IEEE Xplore

Implementation of 1T1R-based OxRRAM Memristor Model for Circuit Design and Simulation


Abstract:

The new emergent memristor can provide non-volatile memory storage, but also an intrinsic computation for matrix-vector multiplication, ideal for low-power, high-speed da...Show More

Abstract:

The new emergent memristor can provide non-volatile memory storage, but also an intrinsic computation for matrix-vector multiplication, ideal for low-power, high-speed data analysis accelerators carried out in memory. Several memristor models have been investigated up to now. Although, a compact model needs to be flexible, general, and sufficiently accurate. In this paper, a comparative analysis of a proposed Verilog-A and SPICE memristor models is discussed, in order to elaborate an appropriate model for implementation in CMOSbased circuit applications. An analysis of a Verilog-A memristor model is discussed in order to check the model behavior in ITIR OxRRAM configuration and validating the comparison at circuit level. Two cases are considered using this cell either as a PROM or as an EEPROM. Hence, this analysis generated using Spectre circuit simulator. Our simulation results carry the desired nonlinear memristor fingerprint, and the applicability to fit and simulate different switching behaviors. These results are verified by both electrical and experimental characterization data.
Date of Conference: 02-04 July 2019
Date Added to IEEE Xplore: 19 March 2020
ISBN Information:
Conference Location: Grenoble, France

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