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A High Frequency CMRR improvement technique for Differential Amplifiers in 45nm CMOS | IEEE Conference Publication | IEEE Xplore

A High Frequency CMRR improvement technique for Differential Amplifiers in 45nm CMOS


Abstract:

In this article, a technique has been proposed to extend the common-mode rejection ratio (CMRR) bandwidth of a CMOS differential amplifier. This technique is based on a p...Show More

Abstract:

In this article, a technique has been proposed to extend the common-mode rejection ratio (CMRR) bandwidth of a CMOS differential amplifier. This technique is based on a pole-zero cancellation technique to cancel the dominate pole in the CMRR Transfer function. The differential amplifier tail node swing has been derived under component mismatch conditions, and formulated design methodology for better CMRR. The Circuit has been implemented in 45nm CMOS technology, and simulation results shows CMRR of 114dB at low frequency and 3-dB bandwidth of 30KHz has been achieved, which is approximately 3 times better than conventional technique.
Date of Conference: 06-08 July 2019
Date Added to IEEE Xplore: 30 December 2019
ISBN Information:
Conference Location: Kanpur, India

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