This research introduces a novel sequential type Phase-Frequency Detector (PFD) that is appropriate for low-power and high-frequency PLL applications. This PFD uses a modified True Single Phase Clock (TSPC) based DFF logic to make the above applications worthwhile. The simulation of the proposed PFD is done on cadence software using 90nm CMOS process. The proposed PFD's maximum power consumption is 471.71µW which is achieved at an operating frequency of 1GHz, which shows the efficiency of the designed PFD. The determined phase-noise value is - 140.28dBc/Hz@1MHz offset, which makes the proposed PFD ideal for low-noise PLL applications as well.