Abstract:
This paper presents a novel delay-insensitive three dimension pipeline array multiplier. The organization combines deep (gate-level) pipelining of Manchester adders with ...Show MoreMetadata
Abstract:
This paper presents a novel delay-insensitive three dimension pipeline array multiplier. The organization combines deep (gate-level) pipelining of Manchester adders with a two dimensional cross-pipeline mesh for multiplicand and multiplier propagation and partial product bits calculation. Fine grain pipelining with elimination of broadcasting and completion trees leads to high-throughput without use of dynamic logic that leaves the door open for further improvement of performance.
Published in: Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors
Date of Conference: 18-18 September 2002
Date Added to IEEE Xplore: 06 January 2003
Print ISBN:0-7695-1700-5
Print ISSN: 1063-6404