This paper presents a hardware design for a scalable, high throughput, configurable LFSR. High throughput is achieved by producing L consecutive outputs per clock cycle with a clock cycle period that, for practical cases, increases only logarithmically with the block size L and the length of the register N. Flexibility is ensured by offering full reconfigurability of the generator polynomial within 1 clock cycle. At the heart of the design is a decomposition of the block-based state-update transition-matrix into two matrices, which enables an efficient implementation in terms of both latency and area. Potential target applications for this design include PN sequence generation in CDMA systems, BIST for VLSI circuits, CRC, encryption and error correction.