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Hierarchical modeling of Phase Change memory for reliable design | IEEE Conference Publication | IEEE Xplore

Hierarchical modeling of Phase Change memory for reliable design


Abstract:

As CMOS based memory devices near their end, memory technologies, such as Phase Change Random Access Memory (PRAM), have emerged as viable alternatives. This work develop...Show More

Abstract:

As CMOS based memory devices near their end, memory technologies, such as Phase Change Random Access Memory (PRAM), have emerged as viable alternatives. This work develops a hierarchical modeling framework that connects the unique device physics of PRAM with its circuit and state transition properties. Such an approach enables design exploration at various levels in order to optimize the performance and yield. By providing a complete set of compact models, it supports SPICE simulation of PRAM in the presence of process variations and temporal degradation. Furthermore, this work proposes a new metric, State Transition Curve (STC) that supports the assessment of other performance metrics (e.g., power, speed, yield, etc.), helping gain valuable insights on PRAM reliability.
Date of Conference: 30 September 2012 - 03 October 2012
Date Added to IEEE Xplore: 13 December 2012
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Conference Location: Montreal, QC, Canada

References

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