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Post-layout OPE-predicted redundant wire insertion for clock skew minimization | IEEE Conference Publication | IEEE Xplore

Post-layout OPE-predicted redundant wire insertion for clock skew minimization


Abstract:

Based on the equilibrium concept of inserting load in a physical balance, the insertion of redundant wires can be used to minimize the clock skew in an OPE-predicted cloc...Show More

Abstract:

Based on the equilibrium concept of inserting load in a physical balance, the insertion of redundant wires can be used to minimize the clock skew in an OPE-predicted clock tree. For five tested benchmarks, the experimental results show that our proposed algorithm only increases 2.8% of the total load on the average for the insertion of OPE-predicted redundant wires and decreases 30.85 ps of the clock skew on the average to obtain the near zero-skew result in reasonable CPU time.
Date of Conference: 30 September 2012 - 03 October 2012
Date Added to IEEE Xplore: 13 December 2012
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ISSN Information:

Conference Location: Montreal, QC, Canada

References

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