In this paper, we propose an efficient motion estimation hardware architecture for High Efficiency Video Coding (HEVC) using a Modified Reference Data Access Skip (MRDAS) for reducing the minimum memory bandwidth. The memory bandwidth is responsible for the throughput limitations in motion estimation, especially when dealing with high quality video of a large frame size and search range. This architecture is designed for reducing the memory bandwidth using a memory access sequence and MRDAS. We save about 80% of the memory access cycles for the reference data compared to a conventional method with about 0.2 dB video quality degradation. The architecture is designed in Verilog HDL with a 65 nm cell library. The simulation results show that the architecture can achieve real-time processing of a 3,840 × 2,160 video image size at 30 fps at 350 MHz.