Abstract:
Two proposed divide-by-4/5 dual-modulus prescaler (DMP) based on the true single-phase clock (TSPC) and extended TSPC (E-TSPC) structure for the 5G applications is design...Show MoreMetadata
Abstract:
Two proposed divide-by-4/5 dual-modulus prescaler (DMP) based on the true single-phase clock (TSPC) and extended TSPC (E-TSPC) structure for the 5G applications is designed by TSMC 180nm CMOS technology. The TSPC DMP achieves a maximum operating frequency of 4.9GHz with 4.4GHz bandwidth and consumes 0.72mW at 1.8V. The maximum operating frequency of E-TSPC DMP is up to 7.6GHz with 5.3GHz bandwidth and consumes 1.29mW.
Date of Conference: 17-19 July 2023
Date Added to IEEE Xplore: 31 August 2023
ISBN Information:
Contents 