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AVS3 Decoder Architecture and VLSI Implementation for 8K UHDTV Application | IEEE Conference Publication | IEEE Xplore

AVS3 Decoder Architecture and VLSI Implementation for 8K UHDTV Application


Abstract:

In this paper we propose video decoder architecture using homogeneous decoder core in parallel for 8K video. This architecture is applied to implement the third generatio...Show More

Abstract:

In this paper we propose video decoder architecture using homogeneous decoder core in parallel for 8K video. This architecture is applied to implement the third generation of audio video coding standard, also known as AVS3, the latest audio video coding standard developed by China AVS working group. The generated video sequences are evaluated in an external SDRAM access latency environment of 900 nsec and performance of 78 frames per second for 8K resolution video is achieved.
Date of Conference: 07-09 January 2022
Date Added to IEEE Xplore: 15 March 2022
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Conference Location: Las Vegas, NV, USA

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