One of the most important performance index of UHF RFID tags is the operating distance, which can be extended by reducing the power consumption of RFID tags. In this paper, an RFID chip based on EPC Class -1 Generation-2/ISOIS000-6C protocol is presented. An optimization method for dynamic power consumption of clock tree in digital back-end design is proposed. This method can further reduce the dynamic power consumption for the completed layout. Under the condition of return frequency 170kHz, the simulated power consumption is reduced from 1. 4S3uW to 1. 357uW for the chip which was taped out with the TSMC 0. 18um process.