Satellite-borne data encryption is one of the main methods to ensure the security of satellite tracking, telemetry and command (TT&C) data communication. However, during the on-orbit execution of the encryption algorithm, the single event upset (SEU) may cause bit flips in memory, and the single-bit errors will spread with the execution of the algorithm, resulting in a large number of errors in the output result. To achieve reliable on-orbit encryption of satellite TT&C data, this paper proposes an efficient and reliable satellite-borne hardware design of Zu Chongzhi (ZUC) stream cipher algorithm, which is implemented on an FPGA platform. Firstly, this paper proposes an alternating processing structure of ZUC stream cipher algorithm using pipeline and 2-slow retiming techniques. This structure mitigates the efficiency degradation of the algorithm caused by the fault-tolerant structure and enhances the execution efficiency in the initialization stage and throughput of the algorithm. Secondly, to solve the problem of algorithm execution errors caused by SEU, this paper uses a Hamming code to provide register-level fault tolerance, which can correct single-bit errors of registers in time and reduce the error probability of output results. The proposed structure not only enhances the reliability of output results, but also reduces the efficiency loss caused by the fault-tolerant structure, and provides the satellite with reliable on-orbit encryption capability for TT&C data secure communication.