In this paper, a novel phase noise mitigation architecture is proposed for a 2×2 MIMO full-duplex transceiver. To compensate for the phase noise in the received self-interference signal, the proposed architecture deploys a delayed version of the transmit oscillator signal as the receive oscillator signal. An optimal oscillator delay configuration is investigated to minimize the power of residual self-interference. Compared to the architecture with one common oscillator for transmitter and receiver, the power of residual SI signal is around 8 dB lower in the case of interference-noise ratio being 60 dB.