Design and Performance Analysis of Enhanced Op-Amp for Low Pass Filter in Subwoofer | IEEE Conference Publication | IEEE Xplore

Design and Performance Analysis of Enhanced Op-Amp for Low Pass Filter in Subwoofer


Abstract:

This project initiates a new modified current differencing stage for an enhanced operational amplifier (op-amp) to implement a low pass filter which is used for subwoofer...Show More

Abstract:

This project initiates a new modified current differencing stage for an enhanced operational amplifier (op-amp) to implement a low pass filter which is used for subwoofer design. Bulk Driven Floating Gate cascode regulated current mirror (BDFG-CRCC) and differential pair amplifier are both techniques used to build a current differencing stage and different blocks such as gain stage, and output stage are used to design the enhanced op-amp. The design of the enhanced op-amp is mainly focused on low-power and area applications, as well as on low-pass filter implementation. The complete enhanced op-amp produces high voltage gain, low noise, suitable input and output impedance, and is compatible with the power supply requirements. The proposed circuit's functionality has been verified using the Cadence Virtuoso platform, specifically in 180 nm GPDK with CMOS and DTMOS technology. The results obtained from simulating the proposed current differencing stage demonstrate better performance when contrasted with an extremely low voltage high compliance current mirror (ELVHC CM)-based current differencing block. As the proposed op-amp demonstrates the power of 497.5m W and 30 transistors were only used to reduce the area. When it is compared with the extremely low voltage high compliance current mirror (ELVHCM) method using op-amp power and area are reduced. The Power-Delay Product (PDP) values of the BDFG method, ELVHCM proposed 1, and ELVHCM proposed 2 methods are as follows: 341.0915E-6 (34.10915%), 309.3031E-6 (30.93031%), and 297.5894E-6 (29.75894%). A lower PDP percentage of the ELHCM proposed 2 methods, such as 29.75894%, is considered better, indicating a more efficient tradeoff between power consumption and delay in the electronic circuit.
Date of Conference: 23-24 April 2024
Date Added to IEEE Xplore: 26 June 2024
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Conference Location: Coimbatore, India

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