A word-parallel, bit-serial signature processor for superimposed coding | IEEE Conference Publication | IEEE Xplore

A word-parallel, bit-serial signature processor for superimposed coding


Abstract:

The design of a word-parallel, bit-serial (WPBS) signature processor for searching superimposed codes is presented. The WPBS signature processor is based on a transposed ...Show More

Abstract:

The design of a word-parallel, bit-serial (WPBS) signature processor for searching superimposed codes is presented. The WPBS signature processor is based on a transposed file organization and is optimal in the sense that the smallest possible amount of data is read. As such, it performs much faster than the word-serial, bit-parallel (WSBP) signature processor proposed in the literature. In addition, it can easily accommodate signatures of different lengths in the same signature store. This feature is important in utilizing the signature store efficiently but difficult to implement with a WSBP architecture. We also discuss the implementation of the processor with magnetic bubble memory.
Date of Conference: 05-07 February 1986
Date Added to IEEE Xplore: 17 September 2015
Print ISBN:978-0-8186-0655-7
Conference Location: Los Angeles, CA, USA