Delay due to on-chip interconnections has become a critical factor for high performance designs in the last years. In modern deep submicron (DSM) technologies wire load and hence wire delays have become dominant over gate delays. Consequently, the influence of wire load models on logic synthesis has increased. This paper presents a novel design flow that enables a better forecast on layout characteristics by computing a wire load model which considers the influence of metal layer properties on the net load. The presented calculation of the wire load could be applied after logic synthesis and cell placement, or it could be integrated in concurrent synthesis and placement tools in order to address the emerging problems of deep submicron designs.