Abstract:
We evaluate Elmore-based Interconnect Delay Models under nanoscale technology parameters. Due to a large delay overestimation Elmore delay provides at specific nodes, som...Show MoreMetadata
Abstract:
We evaluate Elmore-based Interconnect Delay Models under nanoscale technology parameters. Due to a large delay overestimation Elmore delay provides at specific nodes, some attempts to provide more accurate models have been made. However, without reasonable parameters corresponding to actual cmos processes generations, the evaluation of the derived models is potentially dubitable. With technology parameters corresponding to the smaller feature sizes available, we evaluate the ac-curacy of Elmore-based delay models in nowadays VLSI scenarios. Besides an overview of the delay models behavior along technological scaling, we measure the different accuracy for intermediate/local and long/global interconnects.
Published in: 2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)
Date of Conference: 13-16 December 2009
Date Added to IEEE Xplore: 17 February 2010
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