Digital Signal Processing (DSP) applications are widely used from wireless communications to automotive. Their ever growing complexity and throughput still require significant parts to be implemented as dedicated hardware accelerators. A High-Level Synthesis (HLS) flow to automatically generate hardware accelerators for DSP applications is proposed in this paper. By considering bit-width information during all the synthesis process both area and power consumption are optimized. Experimental results show that the proposed approach allows to generate architectures that offer better computation accuracy for a given area and/or power consumption. Effectiveness of the approach is shown through several design experiments in the DSP domain realized on a Xilinx Virtex-5 FPGA.