A full digital low power dpsk demodulator and clock recovery circuit for high data rate neural implants | IEEE Conference Publication | IEEE Xplore

A full digital low power dpsk demodulator and clock recovery circuit for high data rate neural implants


Abstract:

A novel full digital and non-coherent DPSK demodulator is presented for inductively powered biomedical systems. The transmitter uses differential phase encoding technique...Show More

Abstract:

A novel full digital and non-coherent DPSK demodulator is presented for inductively powered biomedical systems. The transmitter uses differential phase encoding technique that requires in the demodulation, a precise symbol clock recovery. This was achieved by the detection of the rising and falling edges of the digitized received carrier. Very low power consumption and high data transmission rate are obtained with an excellent data-rate-to-carrier-frequency ratio of 100% without increasing the carrier frequency. The proposed demodulator is especially appropriate for high data rate biomedical applications such as visual prostheses and brain-machine interface. The circuit is designed in the 0.35-μm CMOS technology of Austria Micro Systems and it consumes 136.3μW @ 3.3 V at a data transmission rate of 10 Mbps.
Date of Conference: 12-15 December 2010
Date Added to IEEE Xplore: 07 March 2011
ISBN Information:
Conference Location: Athens, Greece

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