The efficient use of the power budget in small satellite applications is of primary importance because of the reduced size of the power sources. Unfortunately, high efficiency in power amplifiers (PA) is strongly related to non-linearities and hence distortion. In this paper a digital architecture for the linearization of switched mode PAs is proposed, and a circuit to detect the phase shift and the CORDIC algorithm to correct that phase as well as to compute the magnitude are developed. The results show that linearity is improved by 20 dB for a system with a bandwidth of 9.6 kHz for a loop gain of 10 and 400 ns of system delay. The circuit, synthesized in a FPGA consumes a total of 33.3 mW.