In modern multimedia applications there is a constant increase of the need for more computational power, flexibility and memory availability. The answer for this demand comes from MPSoC platforms implemented on powerful FPGA devices, where high performance and a vast system architecture design flexibility is offered. Whilst many groups are targeting their research on developing automated tools for reducing the total time needed from designing to implementing an MPSoC platform on an FPGA, there is insufficient information on how to explore and determine the optimum memory architecture for such systems. This paper presents a design space exploration for FPGA-based multiprocessing systems using the Powerstone JPEG decoding algorithm as a case study. We explore algorithm partitioning and system architectures for exploitation of both data and task-level parallelism and we include in our study the parameter of different types of memory architectures offered on an FPGA.