Abstract:
The design and implementation in a 1.2 V, 130 nm CMOS technology of an ADC intended for OFDM UWB signals is described. This ADC is based on parallel, continuous-time ΣΔ m...Show MoreMetadata
Abstract:
The design and implementation in a 1.2 V, 130 nm CMOS technology of an ADC intended for OFDM UWB signals is described. This ADC is based on parallel, continuous-time ΣΔ modulators, and employs an OFDM-optimized NTF, implemented using a 3rd order lowpass and a 4t order bandpass modulator. Both are CRFB structures which use active-RC integrators. “Early DAC” clocking is used to reduce the GBW of opamps. Experimental results show good agreement with both system-level and layout-level simulations, with up to 15 dB DR for QPSK modulation.
Date of Conference: 11-14 December 2011
Date Added to IEEE Xplore: 16 January 2012
ISBN Information: