Asynchronous design techniques are gaining attention in the scientific community for their ability to cope with current technologies' problems that the synchronous paradigm may fail to cope with. In fact, fully synchronous SoCs may soon become unfeasible to build. Among multiple asynchronous design styles, the quasi delay insensitive (QDI) stands out for its robustness to delay variations. When coupled to DI codes like m-of-n and to four-phase handshake protocols, the QDI style produces the dominant asynchronous template currently in use. This paper evaluates the use of the Return-to-One 4-phase handshake protocol on Delay-Insensitive Minterm Synthesis (DIMS) logic blocks. Results point that this protocol leads to significant reductions on power consumption when compared to classic Return-to-Zero protocols. No extra hardware is required by the evaluated protocol, as the only required modification is that OR gates are replaced by AND gates, adding no extra delay to the resulting circuit.