Fault attacks are considered major threat to hardware implementations of cryptographic algorithms. A number of known fault injection attacks against Elliptic Curve Cryptography (ECC) processors exist in the literature. In this paper, we propose a gate level technique to harden the resiliency of an ECC processor against fault attacks. Our technique is specific to integer based arithmetic. The proposed hardening technique is built over the Redundant Signed Digit (RSD) as a carry free arithmetic using One Hot Encoding (OHE) with the introduction of competitive overhead of around 35%. The hardened processor has been implemented in Xilinx Virtex-5 FPGA and was verified against different fault models.