Large-scale neuromorphic systems exploit the rapid development of VLSI technology to emulate a wide variety of contemporary neuroscientific models, providing high integration density and power efficiency. One crucial aspect of these systems is the implementation of a routing architecture for the pulse events produced by the neural computation. In this paper we present such a design capable to successfully handle the routing requirements of an accelerated and multi-node neuromorphic system. Pulses can be duplicated at each node, allowing for a tree-like and parallel routing of neural events to different post-synaptic neuron blocks with configurable propagation delay for each transmission. The proposed link-tag routing technique minimizes the total network traffic. The overall design keeps the utilization of hardware resources low and significantly improves the throughput, which is especially important for an accelerated system.