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Low Power and High Speed Static CMOS Digital Magnitude Comparators | IEEE Conference Publication | IEEE Xplore

Low Power and High Speed Static CMOS Digital Magnitude Comparators


Abstract:

Digital magnitude comparators are of special interest in digital systems as they are used to compare the magnitude (equality, greater than or less than) of two binary num...Show More

Abstract:

Digital magnitude comparators are of special interest in digital systems as they are used to compare the magnitude (equality, greater than or less than) of two binary numbers. In this work, a new architecture for magnitude comparators in static logic is presented. The proposed topology presents superior speed performance and reduced power consumption (that improve as the size of the comparator increases for comparators greater than 8bit) with respect to a state of the art magnitude comparator in the literature.
Date of Conference: 09-12 December 2018
Date Added to IEEE Xplore: 20 January 2019
ISBN Information:
Conference Location: Bordeaux, France

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