Gain-cell embedded DRAM (GC-eDRAM) is an interesting alternative to conventional six-transistor (6T) static random access memory (SRAM) cells, offering higher density, lower leakage, and two-ported operation. However, process scaling and the migration to FinFET technologies have brought new challenges to the design of GC-eDRAM cells, including significant changes in device leakage characteristics, resulting in reduced data retention times (DRTs) and new layout rules, affecting the area benefits of known GC-eDRAM topologies. In this paper, for the first time, we examine different GC-eDRAM topologies in a foundry-based 16 nm FinFET technology. Based on this analysis, we develop a methodology for the best practice design of GC-eDRAM in FinFET technologies, based on the transistor characteristics and layout constraints. The developed methodology demonstrates the potential benefits of GC-eDRAM in 16 nm FinFET technology and beyond.