Most quantum computing platforms are nowadays operating at temperatures of a few Kelvin or lower, and their control and readout electronics are gradually brought close or to the same temperature stages. A pivotal step towards the design of such CMOS circuits is the NMOS and PMOS transistor characterization at cryogenic temperatures. While typically performed in cryogenic probe stations down to liquid helium temperature, the CMOS chip for quantum computing is cooled further along with the qubit sample in dilution refrigerators. Here we propose and discuss a wire-bonded and packaged CMOS characterization setup down to 10mK. Several NMOS and PMOS transistors with various aspect ratios of a 180nm CMOS series die were characterized, to develop a novel PDK model for circuit design.