Power consumption and chip area are the main concerns for biomedical implants. In addition, in advanced technologies, designing voltage references with low sensitivity to power supply is challenging due to short channel effects. In this paper, we explore two new voltage reference designs which are optimized for low power and low sensitivity to power supply variation in the 65 nm CMOS technology. In the first design, two stages of voltage references are used in a cascode architecture and in the second design the voltage reference output is regulated and fed back to the local power supply. These designs show low power consumption as 1.72 and 2.77μW, respectively. In addition, simulation results show that the PSRR is achieved as low as -26.5 and -63 dB, respectively.