Physical register file in processors needs to provide more registers when the issue width and pipeline stages increase. Expansion of the physical register file results in long access delay, larger area, and high-power consumption, which needs carefully considerations in superscalar processor design. This article designs an efficient register-renaming technique. It adopts delayed allocation and register packing techniques to improve the efficiency of physical register files temporally and spatially. Experimental results on BOOMv2 show that when the physical register file contains only 34 registers, this technology can improve the performance by 3.59-4.46 times, which achieves the peak performance with more than 64 physical registers.