Abstract:
This paper describes the design and the measurement results of a two-way transformer based current combining power amplifier in 45-nm SOI CMOS technology for 5G phased-ar...Show MoreMetadata
Abstract:
This paper describes the design and the measurement results of a two-way transformer based current combining power amplifier in 45-nm SOI CMOS technology for 5G phased-array systems. A simplified model for the current combiner and the advantages of using current combining is also discussed. A differential splitter for the input power split is also designed to maintain a differential input operation. The PA stage is a 3-stack amplifier to sustain a higher voltage swing at the output under no breakdown issues and ensure a reliable operation. The two-stage design achieves a 19.6 dBm output 1-dB compression with an efficiency of 23% at P1dB and 25% at Psat with 15 dB of gain. The band of operation is 37-43GHz. the design consumes 128mA from a 1.8V supply. The total area is 0.3\times 0.4\ \text{mm}^{2} without pads.
Date of Conference: 28 November 2021 - 01 December 2021
Date Added to IEEE Xplore: 10 January 2022
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