The adoption of convolutional neural network algorithms requires an increasing number of multiply-and-accumulate operations. Compute-in-memory leverages the spatial arrangement of static random access memory (SRAM) cells to increase parallelism and reduce power consumption, overcoming repeated data access and movement from the memory to the computing unit in von Neumann architectures.In the proposed work, an SRAM cell with six transistors is described, explaining how the multiply-and-accumulate operation is performed and how its architecture is suitable for compute-in-memory. As multiple SRAM cells are accessed at the same time, the importance of static noise margin is discussed in the read and hold operations and the 8T Single-Ended SRAM cell presented to overcome read-disturbance issues.The SRAM cells are designed in 16 nm FinFET CMOS process and simulated to calculate the hold and read static noise margins in the nominal and PVT corners. Specifically, the 6T SRAM cell exhibits nominal hold and read static noise margin values of 355.8 mV and 188.0 mV respectively. The 8T Single-Ended SRAM cell has equivalent nominal hold and read static noise margin values of 354.6 mV, overcoming read disturbance and being a feasible candidate for reliable compute-in-memory arrays.