A multiplier is categorized as the most expensive module in a digital system implementation due to a lot of clock cycles requirement, especially in sequential architecture design. The proposed multiplier design utilized booth multiplier with parallel combinational architecture. The multiplier was designed using 130 nm CMOS technology with full custom layout to achieve area efficiency. The architecture consists of 3 blocks, which are 4 blocks 3-bit encoders, 4 blocks 9-bit decoders, and 3 blocks of 12 bit carry look ahead adders. The verifications were done using DRC (Design Rule Check) and LVS (Layout Versus Schematic). Finally, post layout simulation was done after adding the parasitic information of layout results to check the validity of multiplier functionality, to identify circuit delay, and to measure the maximum frequency. The proposed design successfully operates at 1 MHz with the average delay at 268.210 ns. It is considered as a high-speed component since it utilized combinational architecture, therefore the operation can be done within 1 clock cycle.