Field programmable gate arrays (FPGAs) are a popular platform for evolving digital circuits. FPGAs allow to be reconfigured partially which provides a natural way of establishing candidate solutions. Recent research focuses on the hardware implementation of evolutionary design platforms. Several approaches have been developed for effective establishment and evaluation of candidate solutions in FPGAs. In this paper a new mutation operator is proposed for evolutionary algorithms. The chromosome representing the candidate solution is mutated in such a way that only one configuration frame is required for establishing the mutated candidate solution in hardware. The experimental results confirm that the reduced number of configuration frames and mutations at lower level of granularity ensure faster evolution, generation of more candidate solutions in a given time as well as solutions with better quality.