In this paper, we review the main opportunities brought by 3D-monolithic integration for CMOS device and digital circuit. Simulation results show that 3D monolithic integration can provide up to 30% power reduction at iso-performance and 30% manufacturing cost saving for digital circuits, compared to planar technology, making it an attractive alternative to the straightforward technology scaling. We benchmark the transistor-level and cell-level 3D-monolithic integrations, where the inter-tier vias (3D-contacts) are used intra-cell or inter-cell, respectively. On the one hand, transistor-level 3D-integration can be seen as a full-custom approach, both in terms of technology and circuit design. It promises more performance but at the expense of strong Design/Technology Co-Optimizations. On the other hand, the cell-level 3D-integration ensures a 50% area reduction and a re-use of the technology/design platform. The main technology challenge relative to this integration is the thermal budget constraint of the top-level process integration and the intermediate Back-End-Of-Line (iBEOL) stability. Finally, the total isolation of the top-level transistors integrated in 3D-monolithic raises new opportunities and offers new functionalities like for example an efficient dynamic back-biasing capability.