Inner product is an important operation in image processing applications dealing with discrete orthogonal transforms (DOTs). In this paper, a novel power efficient architecture for the computation of inner product is proposed, along with an analysis of the dynamic power consumption of the proposed algorithm. A comparison is made with the conventional distributed arithmetic (DA) approach for computing the inner product. The proposed architecture has been tested and implemented on the Xilinx Virtex-E FPGA. Results obtained have shown that, the total power consumption and the number of LUT required to implement the design of the proposed algorithm is reduced by 51% and 77% respectively in comparison with the conventional DA approach.