Abstract:
We present the analysis and results for a system on a chip (SoC) software/hardware codesign platform, for parallel coding in JPEG2000 compression standard. We show that t...Show MoreMetadata
Abstract:
We present the analysis and results for a system on a chip (SoC) software/hardware codesign platform, for parallel coding in JPEG2000 compression standard. We show that there are optimum numbers of parallel block coders and scheduling granularity per row of codeblocks. The system was implemented on an Altera NIOS II processor with flexible integrated peripheral.
Published in: 2007 IEEE International Conference on Image Processing
Date of Conference: 16 September 2007 - 19 October 2007
Date Added to IEEE Xplore: 12 November 2007
ISBN Information: