As new non-volatile memories are emerging, it is the right time to re-evaluate the conventional memory hierarchy by considering the potential of utilizing new non-volatile memory components. This research is to design a new PRAM-based main memory structure, supporting the advantages of PRAM while providing performance similar to that of conventional DRAM main memory. To replace conventional DRAMs with non- volatile PRAMs as the main memory components, comparable memory access latency and memory cell endurance should be supported. For these goals, we propose a space effective DRAM adapter for PRAM based main memory system. The DRAM adapter consists of two page-block buffers to assure better use of spatial locality and two filtering buffers for better use of temporal locality. The proposed structure is evaluated by a trace-driven simulator using SPEC CPU 2006 traces. Experimental results show that the proposed DRAM adapter can reduce the access latency by around 60% and can increase lifetime of PRAM by around 20 times in comparison with the PRAM-based main memory without any adapter. Thus, our proposed memory architecture can be used to replace the current DRAM-based main memory system.