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A Novel Prefetch Technique for High Performance Embedded System | IEEE Conference Publication | IEEE Xplore

A Novel Prefetch Technique for High Performance Embedded System


Abstract:

Improving the performance of embedded systems can be supported by increasing the hit rates of last level caches (LLC). To enhance the hit rates of LLC, we propose a new p...Show More

Abstract:

Improving the performance of embedded systems can be supported by increasing the hit rates of last level caches (LLC). To enhance the hit rates of LLC, we propose a new prefetch technique. The proposed prefetch technique can fetch the data from main memory prior to actual requests to reduce the long latency to the main memory. To support the proposed technique, we introduce a new structure, LLC buffer which contains several memory blocks nearby the previous referenced memory block. In case that the LLC capacity is not enough, the proposed prefetch technique can improve the performance of embedded systems significantly.
Date of Conference: 28-30 October 2014
Date Added to IEEE Xplore: 26 January 2015
Electronic ISBN:978-1-4799-6541-0
Conference Location: Beijing, China

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