This paper presents an ultra low-power high-speed dynamic comparator. The proposed dynamic comparator is designed and simulated in a 65-nm CMOS technology. It dissipates 7 μW, 21.1 μW from a 0.9-V supply while operating at 1 GHz, 3 GHz sampling clock respectively. Proposed circuit can work up to 14 GHz. Ultra low power consumption is achieved by utilizing charge-steering concept and proper sizing. Monte Carlo simulations show that the input referred offset contribution of the internal devices is negligible compared to the effect of the input devices which results in 3.8 mV offset and 3 mV kick-back noise.