Abstract:
An energy efficient architecture for the discrete cosine transform is presented. The proposed IP is intended to be used as the transform stage in a mobile H.263 codec. In...Show MoreMetadata
Abstract:
An energy efficient architecture for the discrete cosine transform is presented. The proposed IP is intended to be used as the transform stage in a mobile H.263 codec. In particular, it seems well suited for an FPGA implementation since, after a complete place and route process, it is able to sustain a full-motion PAL video streaming operating at a frequency of 74 MHz with a dynamic power dissipation of just 39 mW.
Date of Conference: 26-29 August 2002
Date Added to IEEE Xplore: 07 November 2002
Print ISBN:0-7803-7304-9