The development of more processing demanding video standards on one hand and the popularity of mobile devices such as digital cameras or wireless videophones on the other hand introduce a need of optimization at the processor level. Reconfigurable systems provide an interesting answer to this problem and several works have explored the possibility of performance and power optimization. The following study focuses on tuning a reconfigurable hardware to the requirements of future media processing, using DSP operators appearing in recent FPGA families as an alternative to the typical ALU based architectures. In this paper, architecture perspectives are proposed with respect to low cost development constraints, backward compatibility, easy coprocessor usage and power / performance enhancement, using a new scalable data representation optimized for quality of service (matching pursuit 3D algorithms).