Abstract:
This paper presents the analysis of a gate-level hardware complexity of SHA-1 and SHA-256. There are several kinds of SHA series' analysis on a hardware point of view but...Show MoreMetadata
Abstract:
This paper presents the analysis of a gate-level hardware complexity of SHA-1 and SHA-256. There are several kinds of SHA series' analysis on a hardware point of view but their analyses can be relatively measured according to the given equipments and facilities. In this paper, we provide a logical approach on hardware complexity analysis in area and time angle defined by the number of transistors needed for its construction and the time needed for the signal change to propagate through gates.
Published in: The International Conference on Information Network 2012
Date of Conference: 01-03 February 2012
Date Added to IEEE Xplore: 09 March 2012
ISBN Information: