Abstract:
The amount of buffers allocated to each NoC channel has a significant performance and power consumption impact. Moreover, when a NoC-based application could present chang...Show MoreMetadata
Abstract:
The amount of buffers allocated to each NoC channel has a significant performance and power consumption impact. Moreover, when a NoC-based application could present changes in the communication pattern, or when a new application could be loaded in a SoC, a NoC design based on the worst case scenario probably will present oversize buffers. Besides, it will cause obvious power implications, or the performance will be compromised, since not enough buffers will be used. A runtime mechanism is required to automatically adapt the buffer size as a function of the actual communication pattern. This paper proposes a control mechanism to resize the buffer of an adaptive router, which is able to monitor the traffic behavior, and change the buffer depth of each channel at runtime. Besides, the dynamic configuration of the buffer depth is done without any pause or interruption in the system. As applications show different traffic behavior at runtime, this solution allows one to obtain gains in throughput and latency under rather different communication loads, since the buffers slots are dynamically allocated to increase router efficiency in the NoC. With the proposed architecture the latency was approximately 80% lower and throughput was increased 2 times, on average, for the same buffer depth. Moreover, the adaptive router allows up to 30% power savings, while maintain the same performance of the equivalent homogeneous router.
Published in: 2010 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation
Date of Conference: 19-22 July 2010
Date Added to IEEE Xplore: 22 November 2010
ISBN Information: