This paper investigates design and implementation of the signal processing unit for the relay node in a two-way relay multiple-input multiple-output spatial division multiplexing (MIMO-SDM) system using physical-layer network coding (PNC), reffered to as MIMO-SDM-PNC. Based on Field-programmable gate array (FPGA) platform, two processing architectures for zero-forcing (ZF) and minimum mean square error (MMSE) detector are proposed for the relay node. Using the standard pipe-lining and the parallel computing methodologies, a novel architecture is developed in order to achieve low latency and low-area occupation for FPGA implementation. The proposed architecture has been composed in Verilog language and synthesized on the ISE tool for Xilinx FPGA Virtex 7. Experimental results demonstrate that the proposed design offers high performance in terms of low latency and high throughput.